Bulk silicon metal oxide semiconductor field effect transistors (MOSFET's) are known to experience problems such as punch-through and latch-up as the device dimensions approach the submicrometer range. Punch-through is an effect found in devices having a short channel length or low channel doping in which, at a sufficient drain voltage, the drain electric field penetrates the source region, thereby effectively forming a current (leakage) path. Latch-up is an effect in complementary MOSFET (CMOS) circuits through which high excess current is generated by positive feedback between coupled parasitic bipolar transistors present in the device. The occurrence of latch-up can permanently damage the circuit or temporarily cause circuit malfunction because of the generation of abnormally large current flow.
Conventionally, attempts have been made to avoid punch-through by increasing substrate doping concentration, using a lightly doped drain-structure and reducing power supply voltage and junction depth (as described by G. Baccarani et al, IEEE Trans. Electron Devices, ED-31, 452 (1981), for example). The first three attempts, however, have resulted in degradation of device characteristics below the threshold voltage as well as degradation of substrate bias sensitivity and transconductance. Attempts to suppress latch-up have traditionally involved the use of a thin, lightly doped epilayer on a heavily doped substrate. Alternatively, latch-up suppression has been attempted using trench isolation or selective epitaxial growth. These approaches were described, for example, by D. B. Estreich in Stanford Electronics Lab., Tech. Report G-201-9, Stanford Univ., Calif. (1980); by R. D. Rung et al. in Tech. Digest, Intern'l Electron Device Meeting, p. 237 (1982); and by J. 0. Borland in Tech. Digest, Intern'l Electron Device Meeting, p. 12 (1987). Unfortunately, the thickness of lightly doped epilayers is limited by the out-diffusion of dopants from the heavily doped substrate, and trench isolation and selective epitaxial growth greatly increase process complexity and cost.
Further shrinkage in device dimensions is expected to require a reduction in power supply voltage. As this occurs, the device threshold voltage must be scaled accordingly in order to maintain the desired gain in current driving capability. Reductions in threshold voltage, however, are known to result in increases in the off state leakage current.
Silicon-on-insulator (SOI) structures are known to offer many advantages over their bulk silicon counterparts. These include the absence of latch-up, low parasitic capacitance, high packing density and process simplicity. It has been recently reported that the floating body effect can be eliminated and desirable device characteristics, (including steep subthreshold slope, high punch-through resistance, reduction of hot-carrier degradation, high mobility, and high transconductance) can be obtained in fully depleted thin film SOI MOSFET's. See, for example, S. D. S. Malhi et al, Tech. Digest, Intern'l Electron Device Meeting, p. 107 (1982); J.-P. Colinge, IEEE Electron Device Lett., EDL-7, 244 (1986); J.-P. Colinge, IEEE Electron Device Lett., EDL-9, 97 (1988); and M. Yoshimi et al., Tech. Digest, Intern'l Electron Device Meeting, p. 640 (1987).
A near-intrinsic thin-film SOI complementary MOSFET having a p.sup.+ polysilicon gate in n-channel devices and an n.sup.+ polysilicon gate in p-channel devices has been suggested in order to obtain enhancement mode operation (see Malhi et al., above). Simulations of these devices, however, indicate that the threshold voltages of these devices are about 0.92 V for n-channel devices and -0.92 V for p-channel devices. Such values are too high to be used effectively in submicrometer devices, especially when using scaled power supply voltages.